1. Field of the Invention
The present invention relates to a semiconductor device having a plurality of semiconductor chips packed in a single package which constitutes a system.
In particular, the present invention relates to a test circuit to be implemented in the foregoing semiconductor device.
2. Description of the Related Art
Semiconductor devices have been recently developed which contain a logic chip, a memory chip, and the like of different process technologies in a single package and operate as a system each. The semiconductor devices of this type are called multi chip packages (hereinafter, referred to as MCPs) or multi chip modules (hereinafter, referred to as MCMs).
In general, semiconductor devices are subjected to a burn-in test in their test process. The burn-in test is an acceleration test in which a plurality of semiconductor devices mounted on a test board are operated at high temperature and high voltage for predetermined time in order to reject initial failures of transistors and the like in a short time.
The test conditions of the burn-in test must be set optimally for each manufacturing process so that initial failures are rejected with reliability. For this reason, the burn-in test conditions differ between logic chips and memory chips. For example, logic chips are burn-in tested at 125° C. Memory chips are burn-in tested at 100° C.
In the case of MCPs implementing a logic chip and a memory chip in a single package, however, both the logic chip and the memory chip must be burned in under the same test condition. If the burn-in test is run on the semiconductor devices under a loose one of the test conditions for the respective chips, initial failures might not be fully rejected of the chips whose test conditions are severer. If the burn-in test is run on the semiconductor devices under a strict one of the test conditions for the respective chips, the chips having loose test conditions undergo excessive stress, which may increase a failure ratio.
To avoid the foregoing problems, MCPs have conventionally implemented logic chips that are manufactured by time-proven processes and thus require no burn-in test, for example. In this case, a 100° C. burn-in test can be conducted to reject initial failures of the memory chips implemented in the MCPs.